Researchers have demonstrated that certain commercially available RISC-V processors are vulnerable to various Spectre attacks, a class of speculative execution vulnerabilities previously associated primarily with x86 and ARM architectures. This finding challenges a common assumption that the simpler design of RISC-V chips made them immune to such flaws.
The study, which has been accepted for the 35th Usenix Security Symposium, identifies specific out-of-order RISC-V processors, namely the SiFive P550 and the T-Head Xuantie C910/C920, as susceptible to all major Spectre variants. In-order RISC-V processors, such as the SiFive U74, Xuantie C906, and C908, did not appear to be vulnerable. While prior academic research had shown some experimental RISC-V processors could be affected, this is the first time commercial silicon has been implicated.
The researchers successfully executed proof-of-concept attacks using Spectre-PHT (Pattern History Table), Spectre-BTB (Branch Target Buffer), Spectre-RSB (Return Stack Buffer), and Spectre-STL (Store To Load) techniques. These attacks achieved high recall rates, up to 100 percent, with precision exceeding 97 percent. As a concrete demonstration, they developed an exploit that could leak arbitrary Linux kernel memory on the Xuantie C910 at a rate of 338 B/s.
Spectre vulnerabilities, first disclosed in 2018, exploit traces left by incorrect speculative execution predictions to bypass memory protections and access sensitive data. Defenses developed for x86 and ARM, such as Indirect Branch Restricted Speculation (IBRS), Indirect Branch Prediction Barrier (IBPB), and Single Thread Indirect Branch Predictor (STIBP), are not directly transferable to RISC-V.
A significant challenge for securing RISC-V against Spectre is the architecture's current lack of introspection interfaces, which are crucial for observing and analyzing microarchitectural features. Furthermore, the diverse nature of the RISC-V hardware ecosystem means that a single, universal mitigation strategy is unlikely to be effective across all implementations.
The researchers, affiliated with the CISPA Helmholtz Center for Information Security and DistriNet at KU Leuven, responsibly disclosed their findings in December of the previous year. Three of their proposed patches have since been merged into the mainline Linux kernel, with two additional patches currently under review.
SiFive has reportedly addressed the P550-specific findings. T-Head (Alibaba) has committed to publishing ad-hoc speculation barriers for their processors at an unspecified future date. The researchers opted not to delay publication given that Spectre has been a known vulnerability for eight years.
The authors of the paper, titled "Spectre on RISC-V Silicon: Attacks and Defenses on Commercial Out-of-Order Processors," include Lukas Gerlach, Marton Bognar, Daniel Weber, Michael Schwarz, and Jo Van Bulck. They emphasize that RISC-V, while inheriting the software and threat models of more mature architectures, currently lacks the accumulated hardening. Closing this gap, they argue, requires not just porting individual mitigations but building the necessary architectural primitives, hardware transparency, and ecosystem-wide tooling for effective Spectre defense.
